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DATA SHEET
PD16435, 16435A
DOT MATRIX LCD CONTROLLER/DRIVER
MOS INTEGRATED CIRCUIT
DESCRIPTION
The PD16435 and 16435A are controllers/drivers for a 119 x 73-dot LCD, and perform LCD full-dot and character composite display by means of control by a microprocessor that has a 4 or 8-bit data bus. A charge pump type DC/DC converter is also incorporated, enabling 3 or 5 V single power supply drive. The PD16435 uses an external reference clock. The PD16435A has the on-chip oscillation circuit (external crystal resonator).
FEATURES
* Can interface to 4 or 8-bit CPU. * Incorporates 119 segment outputs and 73 common outputs. (Display duty selectable from 1/35, 1/37, 1/71, 1/73) * 5 x 7 character font 208 character data configuration character generation ROM and 16 character data configuration character generation RAM, allowing composite full-dot and character display * Incorporates extended display functions such as magnification, lateral scrolling, blink, reverse, etc. * Operating voltage: 2.7 V to 5.5 V * On-chip DC/DC converter: Selectable between x4 set-up circuit and x2 step-up circuit * On-chip temperature correction circuit * Master/slave operation capability * On-chip power-on reset circuit * On-chip oscillation circuit (PD16435A) * 232-pin TCP (Tape Carried Package)
ORDERING INFORMATION
Part Number Package TCP (TAB), Standard ROM code Standard quad TCP (Conforms to EIAJ), Standard ROM code Standard dual TCP (Output OLB: 0.25 mm pitch), Standard ROM code TCP (TAB), Standard ROM code Standard quad TCP (Conforms to EIAJ), Standard ROM code Standard dual TCP (Output OLB: 0.25 mm pitch), Standard ROM code
PD16435N-001-xxx PD16435N-001-001 PD16435N-001-002 PD16435AN-001-xxx PD16435AN-001-001 PD16435AN-001-052
Explanation of Part Number
PD16435 (A) N-xxx-xxx
TCP code ROM code The TCP model is a custom model. For details, consult NEC sales representative.
Document No. S10298EJ3V0DS00 (3rd edition) Date Published April 1997 N Printed in Japan
(c)
1995
PD16435, 16435A
BLOCK DIAGRAM
SEG119 COM73 OSC2 COM1 OSC1 SEG1
OSC
Common Driver
Segment Driver
Timing Generator
73-Bit Shift Register
119-Bit Latch
Scaler
119
Cursor Blinking Control Register
Selector
OSC3
Scroll RAM 13 x 73 Bits
Display RAM 119 x 73 Bits
CGROM 5 x 7 x 208 Bits
5
CGRAM 5 x 7 x 16 Bits Instruction Decoder
8 8 8
Instruction Register
Data Register
Busy Flag
OP-Amp
8
Parallel I/F
x2/x4 Step-Up Circuit
8
GND1
C3+ C3-
VCC
WR
BUSY
RESET
TEST1
SYNC
WS
D0~7
SCR
C2+ C2-
VDD
RS
RD
CS
3/5
TEST2
2
GND2
C1+ C1-
VIN+
- VIN
8
V1 V2 V3 V4 V5
Address Counter
7
5
119
73
SEG30 Dummy5 COM73 Dummy3 Dummy4 SEG1
Dummy13 Dummy1 Dummy2 COM38 COM39 79 1 258 80
PIN CONFIGURATION (CHIP)
Dummy14 SEG31 SEG32
SEG83 SEG84 Dummy15 135
214
PD16435, 16435A
136
Dummy26 VDD GND1 CS RS RD WR WS D0 D1 D2 D3 D4 D5 D6 D7 RESET SCR BUSY SYNC TEST1 TEST2 3/5 OSC1 OSC2 OSC3 VCC Dummy25 C1- C1+ C2- C2+ C3- C3+ VIN(-) VIN(+) GND2 V1 V2 V3 V4 V5 Dummy24 Dummy23 215
SEG85 Dummy16
Dummy17 SEG119
COM37 Dummy20
Dummy22 Dummy21 COM1 COM2
3
PD16435, 16435A
PIN DESCRIPTIONS
Pin Name CS RS Pin No. 255 254 Input/Output Input Input Output Type --- --- Chip select signal Register selection signal (specifies address register when "0", control register when "1"). Read enable signal. Reads write address when scrolling. Active edge is falling edge. Write enable signal. Active edge is falling edge. Word length selection signal (4-bit input when "1", 8-bit input when "0"). Transmit/receive data (3-state bidirectional) Upper D4 to D7 Lower D0 to D3 (These pins should be set as unused in case of 4-bit data). In test mode, these pins are output pins. In a 4-bit transfer, storage is performed in the upper (MSB) in order from the data transferred first. "0" indicates busy state. "0" Initialization of all internal registers and commands is performed. Output is fixed at V1. Signal is output to CPU on completion of one-character scroll. Synchronization signal input/output pins for master/slave operation. Description
RD
253
Input (Schmitt)
---
WR
252
Input (Schmitt)
---
WS
251
Input
---
D0 to D7
250 to 243
Input/output
CMOS 3-state
BUSY RESET SCR SYNC
240 242 241 239
Output Input Output Input/output
Nch open-drain --- CMOS Nch open-drain
OSC1 OSC2
235 234
---
---
PD16435: Input the 4.19 MHz reference clock to the OSC1 pin externally. Leave the OSC2 pin open. (Always outputs high level.) PD16435A: This is the pin to which the 4.19 MHz crystal resonator is connected. Input the external clock to OSC1 first.
2 Hz external clock input pin. Scaled by 2 internally to generate 1 Hz, used as blink synchronization signal. Common output signals
OSC3 COM1 to COM73 SEG1 to SEG119 TEST1 TEST2
233 212 to 176 3 to 38 41 to 70 81 to 134 137 to 171 238 237
Input (Schmitt)
---
Output
Analog switch
Output
Analog switch
Segment output signals "1" Test mode "0" or open Normal operating mode
Output
---
4
PD16435, 16435A
Pin Name V1
Pin No. 221 220 to 217 224 223 232, 256 257, 222
Input/Output Output
Output Type --- LCD drive power supply pin Internal OP-amp output
Description
V2 to V5
Input
---
LCD drive power supply pins Can be adjusted by addition of external resistor.
VIN(-) VIN(+) VCC, GND1 VDD, GND2
Input --- ---
--- --- ---
Liquid crystal drive power supply OP-amp input pins Logic power supply, GND Liquid crystal drive (step-up) power supply, GND Drive voltage selection pin "1" VDD = 3 V (x4 step-up circuit selected) "0" VDD = 5 V (x2 step-up circuit selected) A 1 F tantalum or ceramic capacitor should be connected externally.
3/5
236
Input
---
C1, C2, C3
230 to 225
---
---
REFERENCE CLOCK
Product Name Reference Clock External input On-chip oscillation circuit (External crystal resonator)
PD16435 PD16435A
OSC CIRCUIT (PD16435A)
OSC1
OSC2
4.19 MHz
5
PD16435, 16435A
REGISTER FUNCTIONS
(1) Address Register Sets the address of each register, and also sets display control, standby mode, and scaler resetting.
MSB LSB x : Don't Care
b7 b6 b5 b4 b3 b2 b1 b0
Register address (0H to CH) See table below Display control 00: Display control off (SEGn, COMn = V1) 01: Display control off (SEGn, COMn = unselected waveform) 10: Normal operation 11: Normal operation
Standby mode setting 0: Normal operation 1: Standby mode Note
Blink internal scaler reset and 1/2 scaler reset 0: Normal operation 1: Reset (Blinking starts when it lights.) (Used to synchronize time variations and time mark blinking.)
Note Standby mode =
DC/DC converter stopped OSC1 input invalid ( PD16435) OSC stopped ( PD16435A) SEGn, COMn = V1 Data write/read prohibited
After powering on
0 0 0 0 0 0 0 0
Register address list
Address b3 b2 b1 b0 0000 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Register Name
Full-dot X address register Full-dot Y address register Full-dot data register Character X address register Character Y address register Character data register CGRAM address register CGRAM data register Extension register Extension register X address register Extension register Y address register Scroll register Control register
6
PD16435, 16435A
(2) Full-Dot X Address Register (Register Address = 0000B) Performs full-dot display, display screen X (segment) direction address setting. As scrolling is not possible with a fulldot display, addresses are not allocated to the scroll RAM area.
MSB LSB b3 b2 b1 b0 x : Don't Care
Full-dot X address (00H to 0EH)
After powering on: Undefined (3) Full-Dot Y Address Register (Register Address = 0001B) Performs full-dot display, display screen Y (common) direction address setting.
MSB LSB b6 b5 b4 b3 b2 b1 b0 x : Don't Care
Full-dot Y address (00H to 48H)
After powering on: Undefined (4) Full-Dot Data Register (Register Address = 0010B) Inputs full-dot display data. Display data is stored in the display memory with the MSB on the left, and display data "1" corresponds to illumination.
Full-dot X address = 00H to 0DH MSB LSB
b7 b6 b5 b4 b3 b2 b1 b0
Full-dot display data Full-dot X address = 0EH MSB b7 b6 b5 b4 b3 b2 b1 LSB x : Don't Care
Full-dot display data
After powering on: Undefined
7
PD16435, 16435A
Full-Dot X Address and Y Address Allocation
X Address 00H(1) 01H(2) 0EH(15)
Y Address
00H(1) 01H(2)
48H(73)
b7 b6
b5 b4 b3 b2 b1 b0
b7 b6
b5 b4 b3 b2 b1
8 Bits
7 Bits
(5) Character X Address Register (Register Address = 0011B) Performs character display display, screen X (segment) direction address setting. X addresses include the scroll RAM area.
MSB LSB b4 b3 b2 b1 b0 x : Don't Care
Character X address (00H to 15H)
After powering on: Undefined (6) Character Y Address Register (Register Address = 0100B) Performs character display display, screen Y (common) direction address setting.
MSB
LSB b2 b1 b0 x : Don't Care
Character Y address (00H to 07H)
After powering on: Undefined
8
PD16435, 16435A
(7) Character Data Register (Register Address = 0101B) The character indicated in the character code table is displayed at the position indicated by the character X and Y address registers.
MSB LSB x : Don't Care
b7 b6 b5 b4 b3 b2 b1 b0
Character code
After powering on: Undefined Character X Address and Y Address Allocation
X Address Scroll RAM Area 13H(20) 14H (21) 15H (22)
Y Address
Display RAM Area 00H(1) 01H(2)
00H(1)
01H(2)
1 Bit
07H(8)
8 Bits
1 Bit
5 Bits
9
PD16435, 16435A
(8) CGRAM Address Register (Register Address = 0110B) Performs address setting when display data is written to CGRAM. Bits b6 to b3 of the CGRAM address indicate the character code, and bits b2 to b0 indicate the character line.
MSB LSB b6 b5 b4 b3 b2 b1 b0 x : Don't Care
Line address (00H to 06H)
Note
Character code (00H to 0FH)
Note If auto increment is set with the control register, 06H is followed by 07H. Dummy data should be sent when the address is 07H. Example: (CGRAM address with auto increment) --- 15H 16H 17H 18H --After powering on: Underfined (9) CGRAM Data Register (Register Address = 0111B) CGRAM display data. The lower 5 bits of the write data are valid.
MSB LSB b4 b3 b2 b1 b0 x : Don't Care
CGRAM data
After powering on: Undefined
10
PD16435, 16435A
(10) Extension Register (Register Address = 1000B) Performs magnification, reverse, cursor, and time mark setting.
MSB LSB b3 b2 b1 b0 x : Don't Care
In case of magnification setting 00: Standard 01: x2 horizontal 10: x2 vertical 11: x4 magnification (x2 horizontal & vertical) Magnification display is performed at any line position; characters of different sizes cannot be displayed on the same line. Line specification magnification display is possible by setting an extension Y address after this command, and multiple-line magnification display is possible by setting consecutive extension Y address. In case of reverse setting 00: Reverse cancellation (line specification) 01: Reverse (line specification) 10: Reverse cancellation (full screen) 11: Reverse (full screen) Line specification reverse display is possible by setting an extension Y address after this command, and multiple-line reverse display is possible by setting consecutive extension Y addresses. Regarding the reverse display Y address direction, a total of 9 dots (7 character part dots + 1 cursor part dot + 1 top space dot) are reversed. In the case of x2 vertical magnification or x4 magnification, a total of 18 dots (14 character part dots + 2 cursor part dots + 2 top space dots) are reversed. In case of cursor setting 00: Cursor non-display 01: Cursor display (blinking stopped) 10: Cursor display (blink operation) 11: Don't Care Blinking display can be performed at any address by specifying an extension X and Y address after this command. The specification is for one address only. The address specification should be performed in the order: X address Y address. In case of character blink setting X0: Blinking stopped X1: Blink operation Blinking can be performed at any address by specifying an extension X and Y address after this command. The specification is for one address only. The address specification should be performed in the order: X address Y address. Extension function setting 00: Magnification setting 01: Reverse setting 10: Cursor setting 11: Character blink setting
After powering on
0 0 0 0
11
PD16435, 16435A
Display and RAM Allocation in Case of Magnification Setting (1) Example of x2 horizontal magnification (line 07H specified)
Display 00H(1) 01H(2) 13H(20)
00H(1)
01H(2)
1 Bit
07H(8)
(X=00H)
(X=09H)
8 Bits
10 Bits 2 Bits RAM 00H(1) 01H(2) 13H(20)
1 Bit
14H(21)
15H(22)
00H(1)
01H(2)
Display Area
Non-Display Area
07H(8)
00H
01H
09H
0AH
15H
Note Lines 0AH to 15H for which x2 horizontal magnification is specified can be used as scroll RAM. 12
PD16435, 16435A
(2) Example of x2 vertical magnification (line 00H specified)
Display 00H(1) 01H(2) 13H(20)
00H(1)
16 Bits
2 Bits 01H(2) 1 Bit
06H(7)
5 Bits RAM 00H(1) 01H(2) 13H(20) 14H(21) 15H(22)
00H(1)
01H(2)
Display Area
Non-Display Area
06H(7)
07H(8)
Note If x2 vertical magnification is specified for line 07H, the lower half will be outside the display area. Also, if x2 vertical magnification is specified for line 06H, the bottom dot will be a space.
13
PD16435, 16435A
(3) Example of x4 magnification (line 00H specified)
Display 00H(1) 2 Bits 09H(10) 1 Bit
10 Bits 00H(1) 16 Bits
2 Bits 01H(2) 1 Bit
06H(7)
00H RAM 00H(1)
01H
13H
01H(2)
09H(10) 0AH(11)
14H(21) 15H(22)
00H(1)
01H(2)
Display Area
Non-Display Area
06H(7)
07H(8)
00H
01H
13H
14H
15H
Note Lines 0AH to 15H for which x4 magnification is specified can be used as scroll RAM. If x4 magnification is specified for line 07H, the lower half will be outside the display area, and if x4 magnification is specified for line 06H, the bottom dot will be a space. 14
PD16435, 16435A
(11) Extension X Address Register (Register Address = 1001B) Performs extension display, display screen X (segment) direction address setting. X addresses include the scroll RAM area. This register must be executed before the extension Y address register.
MSB LSB b4 b3 b2 b1 b0 x : Don't Care
Character X address (00H to 15H)
After powering on: Undefined (12) Extension Y Address Register (Register Address = 1010B) Performs extension display, display screen Y (common) direction address setting. This register must be executed after the X address.
MSB LSB b2 b1 b0 x : Don't Care
Character Y address (00H to 07H)
After powering on: Undefined (13) Scroll Register (Register Address = 1011B) Performs scroll setting.
MSB LSB x : Don't Care
b7 b6 b5 b4 b3 b2 b1 b0
Scroll direction setting 00: Scroll reset Note 1 01: Right scroll 10: Left scroll 11: Scrolling stopped Note 2 Scrolling by specification of any line is possible by setting a character Y address after this command. Scrolling can only be performed for one character-unit line. Scroll speed setting (00H to 3FH) This value specifies the number of frames for a one-bit move. If 00H is set, scrolling is stopped.
Notes 1. 2.
When scroll reset is executed, the screen leftmost character X address returns to 00H, and scrolling is stopped. After scrolling has been stopped, character Y address setting is necessary when scrolling is restarted. It is not possible to set a different address from the character Y address before scrolling was stopped.
After powering on
0 0 0 0 0 0 0 0
15
PD16435, 16435A
(14) Control Register (Register Address = 1100B) Performs address increment direction, common output, frame frequency, blinking, and master/slave setting.
MSB LSB x : Don't Care
b7 b6 b5 b4 b3 b2 b1 b0
Address increment direction setting 00: Auto increment in X direction (up-count) 01: Auto increment in Y direction (up-count) 1x: Address retention When auto increment is used, the address is automatically up-counted after a full-dot, character, or CGRAM
Note
data write.
The character X address is reset to 13H. When address retention is specified, the address is retained after a data write.
Common output setting 00: 35 outputs (1/35 duty, COM2 to COM36 selected) 01: 37 outputs (1/37 duty, COM1 to COM37 selected) 10: 71 outputs (1/71 duty, COM2 to COM72 selected) 11: 73 outputs (1/73 duty, COM1 to COM73 selected) Frame frequency setting 00: 100 Hz 01: 75 Hz 10: 50 Hz 11: Don't Care LCD drive is performed by frame inversion. Blink source setting 0: External clock (OSC3) 1: Internal scaled block Master/slave setting 0: Master 1: Slave
Note
CGRAM is incremented in the Y direction even if 00H is set.
After powering on
0 0 0 0 0 0 0 0
16
PD16435, 16435A
Standard ROM Code (001)
Higher Bit Lower 4 Bits Bit 4 Bits
0000 CC RAM (1)
0001
0010
0011
0100
0101
0110
0111
1010
1011
1100
1101
1110
1111
xxxx0000
xxxx0001
(2)
xxxx0010
(3)
xxxx0011
(4)
xxxx0100
(5)
xxxx0101
(6)
xxxx0110
(7)
xxxx0111
(8)
xxxx1000
(9)
xxxx1001
(10)
xxxx1010
(11)
xxxx1011
(12)
xxxx1100
(13)
xxxx1101
(14)
xxxx1110
(15)
xxxx1111
(16)
17
PD16435, 16435A
ABSOLUTE MAXIMUM RATINGS (TA = 25 C, GND1 = GND2 = 0 V)
Parameter Supply voltage 1 (3/5 = L) Supply voltage 2 (3/5 = H) Logic input voltage Logic output voltage LCD drive power supply voltage LCD drive power supply input voltage LCD drive power supply output voltage Amplifier input voltage Driver output voltage (Segment, common) Storage temperature range VCC1 VCC2 VIN VOUT1 VDD V2 to V5 V1 VIN (+), VIN (-) VOUT2 Tstg. Symbol Rating -0.3 to +7.0 -0.3 to +4.0 -0.3 to VCC+0.3 -0.3 to VCC+0.3 VCC-0.3 to +16.0 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -55 to +150 Unit V V V V V V V V V C
RECOMMENDED OPERATING RANGES
Parameter Supply voltage 1 (3/5 = L) Supply voltage 2 (3/5 = H) LCD drive supply voltage Logic input voltage LCD drive power supply input voltage LCD drive power supply output voltage External capacitance Operating temperature range Symbol VCC1 VCC2 VDD VIN V2 to V5 V1 C0 to C3 TA MIN. 4.5 2.7 VCC 0 0 0 1 -40 TYP. 5.0 3.0 8.0 MAX. 5.5 3.6 14.5 VCC VDD VDD 4.7 +85 Unit V V V V V V F C
18
PD16435, 16435A
ELECTRICAL SPECIFICATIONS (Unless specified otherwise, TA = -40 to +85 C, C0 to C3 = 1 F, Vcc = 5 V 10% : 3/5 = L or Vcc = 2.7 V to 3.6 V : 3/5 = H)
Parameter Input voltage high Input voltage low Input voltage high Input voltage low Hysteresis voltage Input current high Symbol VIH1 VIL1 VIH2 VIL2 VH IIH1 OSC3, VIN(+), VIN(-), VIN = VCC CS, RS, RD, WR, WS, RESET, 3/5, Input current low Input current high Input current low Output voltage high IIH1 OSC3, VIN(+), VIN(-), VIN = 0 V IIH2 IIL2 VOH1 IOH = -1 mA Dn, BUSY, SCR, SYNC, 3/5 = L Output voltage low VOL1 IOL = 4 mA Dn, SCK, 3/5 = H Output voltage high VOH2 IOH = -0.6 mA Dn, BUSY, SCR, SYNC, 3/5 = H Output voltage low VOL2 IOL = 2.4 mA V1 pin Output voltage high VOH3 IOH = -1 mA VIN(+) = VDD, VIN(-) = 0 V V1 pin Output voltage low VOL3 IOL = -10 A VIN(+) = 0 V, VIN(-) = VDD Dn, SYNC, BUSY Leak current high ILOH VIN/OUT = VCC Dn, SYNC, BUSY Leak current low Common output RCOM on-resistance Segment output RSEG on-resistance Driver unit supply voltage VDD1 (step-up voltage) Driver unit supply voltage VDD2 (step-up voltage) 3/5 = H 3/5 = L RB = 10 k 3.6VCC 4.0VCC V ILOL VIN/OUT = 0 V COM1 to COM73 |IO| = 100 A SEG1 to SEG119 |IO| = 100 A RB = 10 k 1.9VCC 2.0VCC V 10 k 5 k -10 10 0.1VDD V 0.9VCC V 0.1VCC V 0.9VCC V 0.1VCC V TEST1, TEST2, VIN = VCC TEST1, TEST2, VIN = 0 V Dn, SCR, 3/5 = L 0.9VCC V 6 -100 -1 Test Conditions Except Schmitt inputs Except Schmitt inputs Schmitt inputs Schmitt inputs Schmitt inputs CS, RS, RD, WR, WS, RESET, 3/5, 1 0.05VCC 0.8VCC 0.2VCC 0.2VCC MIN. 0.7VCC 0.3VCC TYP. MAX. Unit V V V V V
A
A
mA
A
A
A
19
PD16435, 16435A
ELECTRICAL SPECIFICATIONS (Unless specified otherwise, TA = -40 to +85 C, C0 to C3 = 1 F, Vcc = 5 V 10% : 3/5 = L or Vcc = 2.7 V to 3.6 V : 3/5 = H)
Parameter Symbol ICC1 fOSC = 4.19 MHz VCC = 5.0 V, no load, 3/5=L ICC2 fOSC = 4.19 MHz Logic consumption current (PD16435) ICC3 VCC = 3.0 V, 3/5=H RB = 10 kNote fOSC = 4.19 MHz VCC = 5.0 V, 3/5=L ICC4 RB = 10 kNote fOSC = 4.19 MHz VCC = 3.0 V, no load, 3/5=H ICC1 fOSC = 4.19 MHz VCC = 5.0 V, no load, 3/5=L ICC2 fOSC = 4.19 MHz Logic consumption current (PD16435A) ICC3 VCC = 3.0 V, 3/5=H RB = 10 kNote fOSC = 4.19 MHz VCC = 5.0 V, 3/5=L ICC4 RB = 10 kNote fOSC = 4.19 MHz 1.05 2 mA 1.5 3 mA 0.65 1.5 mA 0.6 1.5 mA 0.75 1.5 mA 1.3 2.5 mA 0.35 1 mA Test Conditions VCC = 3.0 V, no load, 3/5=H 0.35 1 mA MIN. TYP. MAX. Unit
Note TYP. values are reference values for TA = 25 C.
20
PD16435, 16435A
NOTE MEASUREMENT CIRCUIT
+
-
VIN+
VIN-
V1 RB
V2 RB
V3 RB
V4 RB
V5 RB
VCC
SWITCHING SPECIFICATIONS (Unless specified otherwise, TA = -40 to +85 C, C0 to C3 = 1 F, Vcc = 5 V 10%, RL = 5 k, CL = 150 pF)
Parameter RD data delay time RD data hold time BUSY low-level time BUSY low-level time SCR high-level time Symbol tRDD tRDH tBL tBL tSCR RD Dn RD Dn When full-dot data is written When charactor data is written 10 3 48 100 9 54 550 Test Conditions MIN. TYP. MAX. 150 Unit ns ns CLKNote CLKNote
s
Note CLK = 4/fOSC
21
PD16435, 16435A
REQUIRED TIMING CONDITIONS (Unless specified otherwise, TA = -40 to +85 C, C0 to C3 = 1 F, VCC = 5 V 10%, RL = 5 k, CL = 150 pF)
Parameter Clock frequency High-level clock pulse width Low-level clock pulse width RD high-level width RD low-level width WR high-level width WR low-level width WR - RD time RD - WR time CS, RS setup time CS, RS hold time Input data setup time Input data hold time Symbol fOSC tWHC tWLC tRDH tRDL tWRH tWRL tWRRD tRDWR tCRS tCRH tDS tDH WR RD RD WR CS, RS WR, RD WR, RD CS, RS Dn WR WR Dn Test Conditions MIN. 3.77 100 100 200 200 200 200 200 200 0 300 0 200 TYP. 4.19 MAX. 4.61 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns
PD16435 only PD16435 only PD16435 only
SWITCHING SPECIFICATIONS (Unless specified otherwise, TA = -40 to +85 C, C0 to C3 = 1 F, Vcc = 2.7 to 3.6 V, RL = 5 k, CL = 150 pF)
Parameter RD data delay time RD data hold time BUSY low-level time BUSY low-level time SCR high-level time Symbol tRDD tRDH tBL tBL tSCR RD Dn RD Dn When full-dot data is written When charactor data is written 15 3 48 100 9 54 550 Test Conditions MIN. TYP. MAX. 500 Unit ns ns CLKNote CLKNote
s
Note CLK = 4/fOSC
22
PD16435, 16435A
REQUIRED TIMING CONDITIONS (Unless specified otherwise, TA = -40 to +85 C, C0 to C3 = 1 F, VCC = 2.7 to 3.6 V, RL = 5 k, CL = 150 pF)
Parameter Clock frequency High-level clock pulse width Low-level clock pulse width RD high-level width RD low-level width WR high-level width WR low-level width WR - RD time RD - WR time CS, RS setup time CS, RS hold time Input data setup time Input data hold time Symbol fOSC tWHC tWLC tRDH tRDL tWRH tWRL tWRRD tRDWR tCRS tCRH tDS tDH WR RD RD WR CS, RS WR, RD WR, RD CS, RS Dn WR WR Dn Test Conditions MIN. 3.77 100 100 400 400 400 400 400 400 0 600 0 400 TYP. 4.19 MAX. 4.61 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns
PD16435 only PD16435 only PD16435 only
23
PD16435, 16435A
AC TIMING TEST VOLTAGE
VIH Input VOH Output VOL VIL
AC CHARACTERISTICS WAVEFORM OSC
OSC1 tWHC I/fOSC tWLC
READ TIMING
CS, RS tCRS RD tRDL WR tRDD tRDH tRDH tRDWR tCRH
Dn
WRITE TIMING
CS, RS tCRS WR tWRL RD tDS tDH tWRH tWRRD tCRH
Dn
24
PD16435, 16435A
BUSY
BUSY
tBL
SCR
SCR tSCR
25
PD16435, 16435A
EXAMPLE TEMPERATURE CORRECTION CIRCUIT CONNECTION
+ -
VIN+
VINRt
V1
V2
V3
V4
V5
RB
RB
RB
RB
RB
VCC Rp R1
Rt : Thermistor
26
STANDARD TCP PACKAGE DRAWINGS (PD16435N-001-001, PD16435AN-001-001)
Detail of Test Pad and Alignment Mark
From Pattern Center 16.30 13.475 12.70 P0.40 0.01X60 = 24.00 0.04 11.50 11.50 4.75 0.03 P0.28 0.01X57 = 15.96 0.025 W0.12 0.02 0.142 0.03 13.475 12.70 13.475 12.70 P0.40 11.50 0.50 0.65
90
MAX. 0.9 0.400.015 P0.40 11.50 0.600.015 (0.30) 0.15 0.3 0.3 13.475 12.70
2.25
From Pattern Center
13.475
W0.12 0.02
11.00
11.50
COATING AREA
7.50 18.00 171 8.33 41
212 217 9.50
232
3 257
P0.28 0.01X57 = 15.96 0.025
12.93 -4.6
11.50
12.70
13.475
2.25
1.00
4.00
13.475
31.82 -0.07
+0
+0.04
137 134
81 70
P0.40 0.01X60 = 24.00 0.04
6.00
12.70
1.00
13.475
1.00 Cu
30
PD16435, 16435A
1.42 0.03 3.50
2.25 13.475 14.50
18.00 13.475
+0
2.25
12.1 -4.6 COATING AREA
27
28
D U M M Y D U M M Y S E G 3 2 DUMMY SEG90 SEG91 SEG92 SEG93 SEG94 DUMMY SEG27 DUMMY SEG29 SEG28 SEG31 SEG30 S E G 8 9 DUMMY S E G 8 7 S E G 8 5 S E G 3 6 S E G 3 4 S E G 8 8 S E G 8 6 S E G 8 4 D U M M Y S E G 3 5 S E G 3 3 COM14 COM13 COM12 COM11 COM10 DUMMY C O M 0 9 C O M 0 1 V 0 4 G N D 0 1 C O M 3 8 C O M 4 6 COM47 DUMMY COM49 COM48 COM51 COM50
PD16435, 16435A
D U M M Y
V 0 5
V 0 3
D U M M Y
C S
V D D
D U M M Y
0.03
s4.75
0.03
MAX 0.9
STANDARD TCP PACKAGE DRAWINGS (PD16435N-001-002)
25.55 (50.25)
25.55
24.8 0.3 1.175 0.01 P0.25 0.01X195 = 48.75 0.075 W0.125 0.015 P0.10X71 4.60 4.60 P0.10X65 P0.1013 P0.0964
24.8 0.3 1.175 0.01
10.90
(4.20)
4.465 -2.3
+0
5.05 0.3
4.65
(9.25) 10.90 11.10 P0.1005 137 134 7.50 0.70 P0.10 171 8.33 41 P0.10 232 3 257 P0.1060 (1.50) P0.1 81 70 P0.1003 2.50 2.00 10.00 7.00 6.00 (12.50) 212 217 0.3 0.3 P0.1044 9.00 1.00 6.00 f1.00 Cu (0.70) 3.00 4.00 10.00 10.00 P0.70 0.01X41 = 28.70 0.045 W0.35 0.02 14.7 0.3 (30.00) 31.00 13.00 31.82 -0.07 4.75 (3.80) (0.70) 0.95
+0.04
8.465 -2.3
COATING AREA
+0
s1.42
PD16435, 16435A
14.7 0.3
WINDING WAY
OUTPUT LEADS UNWINDING DIRECTION
3.50
17.50 19.00 12.1 -4.6
+0
FACE(COPPER)
This Figure is shown by Copper side over Polyimide All tolerances unless otherwise specified 0.05 mm. Coner radius is 0.3 mm Max. II Sprocket holes (52.25 mm) for 1 Pattern
Detail of Alignment Mark 2-1.30 Base Hole 2-1.10 Cu 2-1.90 Cu
MATERIAL t=75 mm BASE FILM : UPILEX-S t=12 mm ADHESIVE : EPOXY t=18 mm COPPER FOIL : ELECTROLYSIS Cu : Sn t=MIN 0.25 mm PLATING t=25 mm SOLDER RESIST : EPOXY
COATING AREA
29
2-R1.15 0.3 SR
PD16435, 16435A
Detail of Test Pad and Alignment Mark
from P.C. 25.55 1.175 0.01 0.60 0.015 0.40 0.015 P0.25 0.40 0.30
0.50 0.50
0.125 1.50
(1.40) 1.40 (1.20)
from P.C.
from P.C.
0.10
0.10
0.10
0.20
NC NC COM38 COM39 COM40 COM41 COM42 * * * * COM73 SEG1 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * SEG119 COM37 * * * * COM5 COM4 COM3 COM2 COM1 NC NC
11.10
10.90
DUMMY VDD GND1
CS
RS
RD WR
WS D0 D1 D2 D3 D4 D5 D6 D7
RESET
SCR
BUSY
SYNC TEST1 TEST2 3/5 OSC1 OSC2 OSC3 VCC C1C1+ C2C2+ C3C3+ VIN(-) VIN(+) GND2 V1 V2 V3 V4 V5 DUMMY
30
0.03
s4.75
0.03
MAX 0.9
STANDARD TCP PACKAGE DRAWINGS (PD16435AN-001-052)
25.55 (50.25)
25.55
24.8 0.3 1.175 0.01 P0.25 0.01X195 = 48.75 0.075 W0.125 0.015 P0.10X71 4.60 4.60 P0.10X65 P0.1013 P0.0964
24.8 0.3 1.175 0.01
10.90
(4.20)
4.465 -2.3
+0
5.05 0.3
4.65
(9.25) 10.90 11.10 P0.1005 137 134 7.50 0.70 P0.10 171 8.33 41 P0.10 232 3 257 P0.1060 (1.50) P0.1 81 70 P0.1003 2.50 2.00 10.00 7.00 6.00 (12.50) 212 217 0.3 0.3 P0.1044 9.00 1.00 6.00 f1.00 Cu (0.70) 3.00 4.00 10.00 10.00 P0.70 0.01X41 = 28.70 0.045 W0.35 0.02 14.7 0.3 (30.00) 31.00 13.00 31.82 -0.07 4.75 (3.80) (0.70) 0.95
+0.04
8.465 -2.3
COATING AREA
+0
s1.42
PD16435, 16435A
14.7 0.3
WINDING WAY
OUTPUT LEADS UNWINDING DIRECTION
3.50
17.50 19.00 12.1 -4.6
+0
FACE(COPPER)
This Figure is shown by Copper side over Polyimide All tolerances unless otherwise specified 0.05 mm. Coner radius is 0.3 mm Max. II Sprocket holes (52.25 mm) for 1 Pattern
Detail of Alignment Mark 2-1.30 Base Hole 2-1.10 Cu 2-1.90 Cu
MATERIAL t=75 mm BASE FILM : UPILEX-S t=12 mm ADHESIVE : EPOXY t=18 mm COPPER FOIL : ELECTROLYSIS Cu : Sn t=MIN 0.25 mm PLATING t=25 mm SOLDER RESIST : EPOXY
COATING AREA
31
2-R1.15 0.3 SR
PD16435, 16435A
Detail of Test Pad and Alignment Mark
from P.C. 25.55 1.175 0.01 0.60 0.015 0.40 0.015 P0.25 0.40 0.30
0.50 0.50
0.125 1.50
(1.40) 1.40 (1.20)
from P.C.
from P.C.
0.10
0.10
0.10
0.20
NC NC COM38 COM39 COM40 COM41 COM42 * * * * COM73 SEG1 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * SEG119 COM37 * * * * COM5 COM4 COM3 COM2 COM1 NC NC
11.10
10.90
DUMMY VDD GND1
CS
RS
RD WR
WS D0 D1 D2 D3 D4 D5 D6 D7
RESET
SCR
BUSY
SYNC TEST1 TEST2 3/5 OSC1 OSC2 OSC3 VCC C1C1+ C2C2+ C3C3+ VIN(-) VIN(+) GND2 V1 V2 V3 V4 V5 DUMMY
32
PD16435, 16435A
REFERENCE DOCUMENTS
NEC Semiconductor Device Reliability/Quality Control System Semiconductor Device Mounting Technology Manual (IEI-1212) (C10535E)
33
PD16435, 16435A
[MEMO]
34
PD16435, 16435A
[MEMO]
35
PD16435, 16435A
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96.5
32

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